Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including non-volatile (e.g., flash) memory, random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM).
An SDRAM can output data in bursts of data that are synchronized with a clock signal. In other words, a certain number of memory cells are accessed and their read data are output in one burst. The length of the data burst can be controlled by programming the burst length to the memory device. The burst length can typically be updated dynamically such that burst length control data from a controller instructs the memory device to output read data in a certain burst length.
FIG. 1 illustrates a schematic diagram of a typical prior art circuit for burst length control in a memory device. The circuit can include a command decoder 100 that receives a command from a controller. The command decoder 100 can decode the type of command that was received (e.g., read, write) and output an indication (e.g., RD, WR) of the command type. An OR gate 101 coupled to the output indications can generate a toggle signal that is input to the clock input of an upstream counter 102. The upstream counter 102 can generate a counter output that changes based on the toggle signal input. Only one of the counter outputs is logically high at any one time. The toggle signal input changes which of these outputs goes to a logical high.
The outputs of the upstream counter 102 are each coupled to a different one of a number of latches 103-106. The inputs of each latch 103-106 are coupled to an address signal bit (e.g., A12). The A12 signal is latched into whichever latch 103-106 has a logical high, from the downstream counter 102, coupled to its latch control input (e.g., LAT). The A12 signal can be used by the controller to set the burst length of the memory device.
The latched A12 signal can then be output through an inverter 140 as a BL4ON signal. The BL4ON signal, is a logical high when the burst length is chosen as a burst length of four. The BL4ON signal is a logical low when the burst length is chosen as a burst length of eight.
The particular latch chosen to output its stored data is chosen by a particular output enable signal from a downstream counter 110. The downstream counter 110 is clocked by support circuitry 130 that includes a delay locked loop (DLL) 132 having shift register outputs coupled to a delay line 131 and a DLL output clock coupled to a pair of registers 134, 135. The DLL shift register outputs provide the delay line 131 with the same delay as that being set by the DLL 132. Thus, the delay in the output of the delay line 131 can match the clock delay present in the DLL clock.
The support circuitry 130 further includes a buffer 133 that is controlled by a signal that instructs the buffer 133 whether the signal coupled to the input of the delay line 131 and, thus, to the input of the buffer 133, is a read or write signal. A write signal is output to the write column address strobe latency register (CWL). A read signal is output to the read column address strobe latency (CL) register. The outputs of these registers 134, 135 are input to a logic gate (e.g., NAND) that then clocks the downstream counter 110.
In order to prevent data from being output from the memory device prematurely (e.g., prior to expiration of the CL), the support logic 130 is responsible for taking into account the column address strobe latency prior to allowing the latched A12 signal to be output. Thus, the decoded read or write control signal is input to the support circuitry 130, delayed by the read or write column address strobe latency, then output to clock the downstream counter 110 to enable the next latch 103-106 to output its stored A12 signal.
A problem can result if there is voltage spike on one of the RD or WR signals, if one of the RD or WR signals arrive prior to the DLL achieving a lock, or one of the RD or WR signals being generated prior to the DLL clock being generated. In any of these cases, one of the upstream 102 or downstream counters 110 can get out of synchronization with the other. Once unsynchronized, the latches 103-106 can output the wrong latched A12 signal for controlling the burst length.